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MC74VHC139 Dual 2-to-4 Decoder/ Demultiplexer
The MC74VHC139 is an advanced high speed CMOS 2-to-4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems.
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16 9
SOIC-16 D SUFFIX CASE 751B
VHC139 AWLYYWW
1 8
* * * * * * * * * * * *
16
9
High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 100 FETs or 25 Equivalent Gates Pb-Free Packages are Available*
TSSOP-16 DT SUFFIX CASE 948F
VHC 139 ALYW
1 8
16
9
SOEIAJ-16 M SUFFIX CASE 966 A WL, L YY, Y WW, W
74VHC139 ALYW
1 8
= Assembly Location = Wafer Lot = Year = Work Week
PIN ASSIGNMENT
Ea A0a A1a Y0a Y1a Y2a Y3a GND *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Eb A0b A1b Y0b Y1b Y2b Y3b
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
August, 2004 - Rev. 3
Publication Order Number: MC74VHC139/D
MC74VHC139
ADDRESS INPUTS A0a A1a 2 3 4 5 6 7 1 Y0a Y1a Y2a Y3a ACTIVE-LOW OUTPUTS
Table 1. FUNCTION TABLE
Inputs E H L A1 X L L H H A0 X L H L H Y0 H L H H H Outputs Y1 H H L H H Y2 H H H L H Y3 H H H H L
Ea
L L
ADDRESS INPUTS
A0b A1b
14 13
12 11 10 9
Y0b Y1b Y2b Y3b ACTIVE-LOW OUTPUTS
L
Eb
15
Figure 1. Logic Diagram
En
Y0
A0
Y1
Y2
A1
Y3
Figure 2. Expanded Logic Diagram (1/2 of Device)
A1a INPUT A0a Ea
3 2 1
1 2 EN
X/Y
0 1 2 3
4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b 10 Y2b 9 Y3b
A1a A0a Ea
3 2 1
0 1
DMUX 0 0 G 3 1 2 3
4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b 10 Y2b 9 Y3b
A1b 13 A0b 14 Eb 15
A1b 13 A0b 14 Eb 15
Figure 3. Input Equivalent Circuit
Figure 4. IEC Logic Diagram
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MC74VHC139
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature (C) 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0
NORMALIZED FAILURE RATE
TJ = 130 C
TJ = 120 C
TJ = 100 C
TJ = 110 C
1 1 10 TIME, YEARS 100 1000
Figure 5. Failure Rate vs. Time Junction Temperature
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TJ = 80 C
TJ = 90 C
II I I I I I I I I I I IIIIIIIIIIIII III I I I I I I IIIIIIIIIIIII III I I II I I I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I IIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I II I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I IIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage -0.5 to +7.0 -0.5 to +7.0 Vout IIK DC Output Voltage -0.5 to VCC + 0.5 -20 20 25 75 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package 500 450 mW C Tstg -65 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
II I I I I I IIIIIIIIIIIIIIIIIIIIIII III II II I I I I I I IIIIIIIIIIIIII III I I I I I IIIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIIII III III I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I I I I I I I IIIIIIIIIIIIII III III I
Symbol Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V VCC Vin DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC Operating Temperature -55 0 0 +125 100 20 C tr, tf Input Rise and Fall Time (Figure 3) VCC = 3.3 V 0.3V VCC =5.0 V 0.5V ns/V The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below. FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR
II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII I I I I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I IIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII I I I I II I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I III I I IIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II I I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIII I I I I I I II I I I I II I I I II IIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIII IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
DC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol Symbol CPD tPLH, tPHL tPLH, tPHL CIN ICC IIN VOL VOH VIL VIH Maximum Input Capacitance Maximum Propagation Delay, E to Y Maximum Propagation Delay, A to Y Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Power Dissipation Capacitance (1) Parameter Parameter VCC = 5.0 0.5 VCL = 15 pF CL = 50 pF VCC = 3.3 0.3 VCL = 15 pF CL = 50 pF VCC = 5.0 0.5 VCL = 15 pF CL = 50 pF VCC = 3.3 0.3 VCL = 15 pF CL = 50 pF VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VIN = VCC or GND VIN = 5.5 V or GND VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = - 50 mA Test Conditions Test Conditions VCC (V) 0 to 5.5 5.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHC139
1.5 2.1 3.15 3.85
2.58 3.94
Min
Min
1.9 2.9 4.4
4 TA = 25C TA = 25C Typ Typ 4.4 5.9 6.4 8.9 5.0 6.5 7.2 9.7 0.0 0.0 0.0 2.0 3.0 4.5 4 0.1 9.2 12.7 Max 0.36 0.36 Max 11.0 14.5 0.5 0.9 1.35 1.65 6.3 8.3 7.2 9.2 4.0 0.1 0.1 0.1 10 TA = - 40 to 85C 1.5 2.1 3.15 3.85 2.48 3.80 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.9 2.9 4.4 TA = 85C Typical @ 25C, VCC = 5.0 V 1.0 8.5 10.5 13.0 16.5 Max 40.0 0.44 0.44 Max 11.0 14.5 0.5 0.9 1.35 1.65 7.5 9.5 0.1 0.1 0.1 10 1.5 2.1 3.15 3.85 2.34 3.66 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.9 2.9 4.4 26 TA = - 55 to 125C TA = 125C 1.0 8.5 10.5 13.0 16.5 Max 40.0 0.52 0.52 Max 11.0 14.5 0.5 0.9 1.35 1.65 7.5 9.5 0.1 0.1 0.1 10 pF Unit Unit mA mA pF ns ns V V V V
MC74VHC139
SWITCHING WAVEFORMS
A tPLH Y
50% tPHL 50% VCC
VCC GND
Figure 6.
TEST POINT OUTPUT DEVICE UNDER TEST
E
VCC 50% tPHL tPLH GND
CL*
Y
50% VCC *Includes all probe and jig capacitance
Figure 7.
Figure 8. Test Circuit
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MC74VHC139
ORDERING INFORMATION
Device MC74VHC139D MC74VHC139DR2 MC74VHC139DR2G MC74VHC139DT MC74VHC139DTR2 MC74VHC139M Package SOIC-16 SOIC-16 SOIC-16 (Pb-Free) TSSOP-16 TSSOP-16 (Pb-Free) SOEIAJ-16 Shipping 48 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 50 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC74VHC139
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD N-N FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 -W- G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CE C CE CE C CE
MC74VHC139
PACKAGE DIMENSIONS
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78
INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
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PUBLICATION ORDERING INFORMATION
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